#if defined(TSINGMA_MX) || defined(TSINGMA_GX) || defined(ARCTIC)
/**
   @file sys_tsingma_mx_learning_aging.c

   @date 2019-01-03

   @version v3.0

 */

/****************************************************************************
*
* Header Files
*
****************************************************************************/
#include "ctc_error.h"
#include "ctc_debug.h"

#include "sys_usw_ftm.h"
#include "sys_usw_learning_aging.h"
#include "sys_usw_dma.h"
#include "sys_usw_interrupt.h"
#include "sys_usw_l2_fdb.h"

#include "drv_api.h"

extern sys_learning_aging_master_t* p_usw_la_master[CTC_MAX_LOCAL_CHIP_NUM_PP];
extern int32 sys_tmm_learning_aging_sync_data(uint8 lchip, void* p_info);
extern int32 _sys_usw_aging_get_index_level(uint8 lchip, uint32 key_index, uint8* level);
extern int32 _sys_usw_aging_get_tcam_aging_ptr(uint8 lchip, uint8 domain_type, uint32 key_index, uint32* aging_ptr);
extern sal_mutex_t*             p_learning_cb_mutex ;

/*
 +-----------------------+
 |   TCAM       (8K)     |
 |-----------------------|0
 |   MAC CAM    (32)     |32-1
 |-----------------------|32
 |   MAC0/FLOW0/IP3(16K) |32+32K-1
 |-----------------------|32+64K
 |   MAC1/FLOW1 (16K)    |32+64K+32K-1
 |-----------------------|32+64K+64K
 |   MAC2/FLOW2 (16K)    |32+64K+64K+32K-1
 |-----------------------|32+64K+64K+64K
 |   MAC3/FLOW3 (8K)     |32+64K+64K+64K+32K-1
 |-----------------------|32+64K+64K+64K+64K
 |   MAC4       (8K)     |32+64K+64K+64K+64K+8K-1
 |-----------------------|
 |   MAC5       (8k)     |
 |-----------------------|
 |   flow Cam   (32)     |
 |-----------------------|
 |   host1_da Cam  (16)  |
 |-----------------------|
 |   host1_sa Cam  (16)  |
 +-----------------------+
*/

/* The aging Ptr has already subtracted tcam base!!! */
STATIC int32
_sys_tmm_aging_get_mem_id(uint8 lchip, uint32 aging_idx, uint8 *is_cam, uint8 *type, uint8 *current_level)
{
    uint32 cmd = 0;
    FibAccelerationCtl_m fib_ctl;
    FibHost0HashLookupCtl_m hash_lookup_ctl;
    FibHost1HashLookupCtl_m fib_host1_ctl;

    cmd = DRV_IOR(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &hash_lookup_ctl));

    cmd = DRV_IOR(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_ctl));

    cmd = DRV_IOR(FibHost1HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_host1_ctl));

    if (aging_idx < 32)
    {
        *is_cam = 1;
        *type = SYS_AGING_DOMAIN_MAC_HASH;
    }
    else if ((aging_idx >=  GetFibHost0HashLookupCtl(V, fibHost0IpCamLookupAgingIndexBase_f, &hash_lookup_ctl))
        && (aging_idx <  GetFibHost0HashLookupCtl(V, fibHost0IpCamLookupAgingIndexBase_f, &hash_lookup_ctl) + 32))
    {
        *is_cam = 1;
        *type = SYS_AGING_DOMAIN_IP_HASH;
    }
    else if ((aging_idx >= GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl))
        && (aging_idx < GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32 ))
    {
        *is_cam = 1;
        *type = SYS_AGING_DOMAIN_HOST1;
    }
    else
    {
         if (aging_idx < GetFibAccelerationCtl(V, agingPtrDemarcation0_f, &fib_ctl))
        {
            *current_level = 0;
        }
        else if ((aging_idx >= GetFibAccelerationCtl(V, agingPtrDemarcation0_f, &fib_ctl))
            && (aging_idx < GetFibAccelerationCtl(V, agingPtrDemarcation1_f, &fib_ctl)))
        {
            *current_level = 1;
        }
        else if ((aging_idx >= GetFibAccelerationCtl(V, agingPtrDemarcation1_f, &fib_ctl))
            && (aging_idx < GetFibAccelerationCtl(V, agingPtrDemarcation2_f, &fib_ctl)))
        {
            *current_level = 2;
        }
        else if ((aging_idx >= GetFibAccelerationCtl(V, agingPtrDemarcation2_f, &fib_ctl))
            && (aging_idx < GetFibAccelerationCtl(V, agingPtrDemarcation3_f, &fib_ctl)))
        {
            *current_level = 3;
        }
        else if ((aging_idx >= GetFibAccelerationCtl(V, agingPtrDemarcation3_f, &fib_ctl))
            && (aging_idx < GetFibAccelerationCtl(V, agingPtrDemarcation4_f, &fib_ctl)))
        {
            *current_level = 4;
        }
        else if ((aging_idx >= GetFibAccelerationCtl(V, agingPtrDemarcation4_f, &fib_ctl))
            && (aging_idx < GetFibAccelerationCtl(V, agingPtrDemarcation5_f, &fib_ctl)))
        {
            *current_level = 5;
        }
        else if ((aging_idx >= GetFibAccelerationCtl(V, agingPtrDemarcation5_f, &fib_ctl))
            && (aging_idx < GetFibAccelerationCtl(V, agingPtrDemarcation6_f, &fib_ctl)))
        {
            *current_level = 6;
        }
        else if ((aging_idx >= GetFibAccelerationCtl(V, agingPtrDemarcation6_f, &fib_ctl))
            && (aging_idx < (GetFibAccelerationCtl(V, agingPtrDemarcation6_f, &fib_ctl) + 16 * 1024)))
        {
            *current_level = 7;
        }
        else if ((aging_idx >= (GetFibAccelerationCtl(V, agingPtrDemarcation6_f, &fib_ctl) + 16 * 1024))
            && (aging_idx < (GetFibAccelerationCtl(V, agingPtrDemarcation6_f, &fib_ctl) + 32 * 1024)))
        {
            *current_level = 8;
        }
        else if ((aging_idx >= (GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32))
            && (aging_idx < (GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32 + GetFibHost1HashLookupCtl(V, fibHost1Level1AgingIndexBase_f, &fib_host1_ctl))))
        {
            *current_level = 14;
        }
        else if ((aging_idx >= (GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32 + GetFibHost1HashLookupCtl(V, fibHost1Level1AgingIndexBase_f, &fib_host1_ctl)))
            && (aging_idx < (GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32 + GetFibHost1HashLookupCtl(V, fibHost1Level2AgingIndexBase_f, &fib_host1_ctl))))
        {
            *current_level = 15;
        }
        else if ((aging_idx >= (GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32 + GetFibHost1HashLookupCtl(V, fibHost1Level2AgingIndexBase_f, &fib_host1_ctl)))
            && (aging_idx < (GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32 + GetFibHost1HashLookupCtl(V, fibHost1Level3AgingIndexBase_f, &fib_host1_ctl))))
        {
            *current_level = 16;
        }
        else if ((aging_idx >= (GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32 + GetFibHost1HashLookupCtl(V, fibHost1Level3AgingIndexBase_f, &fib_host1_ctl)))
            && (aging_idx < (GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &fib_host1_ctl) + 32 + GetFibHost1HashLookupCtl(V, fibHost1Level3AgingIndexBase_f, &fib_host1_ctl) + 8 * 1024)))
        {
            *current_level = 17;
        }
        else
        {
            SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "[Aging]The aging ptr is out of range!\n");
            return CTC_E_INVALID_PARAM;
        }
     }

    return CTC_E_NONE;
}
STATIC int32
_sys_tmm_aging_get_level_free_agingptr_to_db(uint8 lchip, uint32* p_level_free_index)
{
    uint8  level_id = 0;
    uint8  step = FibAccelerationCtl_host0Level1MacHashEn_f - FibAccelerationCtl_host0Level0MacHashEn_f;
    uint8  step1 = FibAccelerationCtl_host0MaxFreeNumOnLevel_1_coupleNumber_f - FibAccelerationCtl_host0MaxFreeNumOnLevel_0_coupleNumber_f;
    uint32 hash_en = 0;
    uint32 couple_mode = 0;
    uint32 couple_num = 0;
    uint32 no_couple_num = 0;
    uint32 unused_num = 0;
    uint32 cmd = 0;
    FibAccelerationCtl_m fib_ctl;

    cmd = DRV_IOR(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0,cmd, &fib_ctl));

    for (level_id = 0; level_id < 6; level_id++)
    {
        DRV_IOR_FIELD(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level0MacHashEn_f + step * level_id, &hash_en, &fib_ctl);
        DRV_IOR_FIELD(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0Level0SizeMode_f + step * level_id, &couple_mode, &fib_ctl);

        DRV_IOR_FIELD(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_0_coupleNumber_f + step1 * level_id, &couple_num, &fib_ctl);/* step need re check */
        DRV_IOR_FIELD(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_0_nonCoupleNumber_f + step1 * level_id, &no_couple_num, &fib_ctl);
        DRV_IOR_FIELD(lchip, FibAccelerationCtl_t, FibAccelerationCtl_host0MaxFreeNumOnLevel_0_unusedNumber_f + step1 * level_id, &unused_num, &fib_ctl);

        p_level_free_index[level_id] = hash_en ? (couple_mode ? couple_num : no_couple_num ) : unused_num;
        p_level_free_index[level_id] *= 1024;
    }
    return CTC_E_NONE;
}

int32
sys_tmm_aging_set_register(uint8 lchip)
{
    /* TsingMa.MX
    LPM TCAM: 1024*32
    --------------------------   0
    lpm tcam
    --------------------------   32k
    total: 32,768 aging entry


    INTERNAL: 3,8916*32
    --------------------------   0
    fibhost0 mac cam
    --------------------------   32
    internal 2R memory 000-001
    --------------------------   32 + 64k
    internal 2R memory 100-102
    --------------------------   32 + 640k
    internal 2R memory 103-104
    --------------------------   32 + 1152k
    internal 2R memory 110-111
    --------------------------   32 + 1152k + 32k
    fib host0 internal ip cam
    --------------------------   32 + 1152k + 32k + 32
    flow hash cam
    --------------------------   32 + 1152k + 32k + 32 + 32
    fib host1 cam
    --------------------------   32 + 1152k + 32k + 32 + 32 + 32
    internal 1R memory 205-208
    --------------------------   32 + 1152k + 32k + 32 + 32 + 32 + 32k
    total: 1,245,312 aging entry
    */

    /* TsingMa.GX
    LPM TCAM: 1024*16
    --------------------------   0
    lpm tcam
    --------------------------   16k
    total: 16,384 aging entry


    INTERNAL: 24,580*32
    --------------------------   0
    fibhost0 mac cam
    --------------------------   32
    internal 2R memory 000-001
    --------------------------   32 + 128k
    internal 2R memory 100-102
    --------------------------   32 + 416k
    internal 2R memory 103-104
    --------------------------   32 + 672k
    internal 2R memory 110-111
    --------------------------   32 + 672k + 64k
    fib host0 internal ip cam
    --------------------------   32 + 672k + 64k + 32
    flow hash cam
    --------------------------   32 + 672k + 64k + 32 + 32
    fib host1 cam
    --------------------------   32 + 672k + 64k + 32 + 32 + 32
    internal 1R memory 205-208
    --------------------------   32 + 672k + 64k + 32 + 32 + 32 + 32k
    total: 786,560 aging entry
    */

    uint8  loop = 0;
    uint32 cmd = 0;
    uint32 value = 0;
    uint32 agingPtr_arr[10] = {64, 256, 448, 640, 896, 160, 352, 544, 768, 1024};
    uint32 agingPtr_arr1[10] = {128, 224, 320, 416, 544, 176, 272, 368, 464, 592};
    uint32 min_ptr = 0;
    uint32 max_ptr = 0;
    FibAccelerationCtl_m fib_acc_ctl;
    NeoLpmCtl_m neo_Lpm_ctl;
    IpeAgingCtl_m ipe_aging_ctl;
    FibHost0HashLookupCtl_m host0_lookup_ctl;
    FibHost1HashLookupCtl_m host1_lookup_ctl;
    DynamicFibKeyDsAgingAntFlowIndexCam_m antflow_age_cam;
    uint32 aging_base = 0;
    IpeEcmpCtl_m ipe_ecmp_ctl;
    LagEngineCtl_m lag_engine_ctl;


    cmd = DRV_IOR(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_acc_ctl));

    if (DRV_IS_TMM(lchip))
    {
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_coupleNumber_f, &fib_acc_ctl, 0);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_nonCoupleNumber_f, &fib_acc_ctl, 16);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_unusedNumber_f, &fib_acc_ctl, 32);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_coupleNumber_f, &fib_acc_ctl, 0);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_nonCoupleNumber_f, &fib_acc_ctl, 16);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_unusedNumber_f, &fib_acc_ctl, 32);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_coupleNumber_f, &fib_acc_ctl, 64);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_nonCoupleNumber_f, &fib_acc_ctl, 128);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_unusedNumber_f, &fib_acc_ctl, 192);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_coupleNumber_f, &fib_acc_ctl, 64);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_nonCoupleNumber_f, &fib_acc_ctl, 128);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_unusedNumber_f, &fib_acc_ctl, 192);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_coupleNumber_f, &fib_acc_ctl, 64);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_nonCoupleNumber_f, &fib_acc_ctl, 128);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_unusedNumber_f, &fib_acc_ctl, 192);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_5_coupleNumber_f, &fib_acc_ctl, 128);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_5_nonCoupleNumber_f, &fib_acc_ctl, 192);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_5_unusedNumber_f, &fib_acc_ctl, 256);

        SetFibAccelerationCtl(V, agingPtrDemarcation0_f, &fib_acc_ctl, 32   * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation1_f, &fib_acc_ctl, 64   * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation2_f, &fib_acc_ctl, 256  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation3_f, &fib_acc_ctl, 448  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation4_f, &fib_acc_ctl, 640  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation5_f, &fib_acc_ctl, 896  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation6_f, &fib_acc_ctl, 1152 * 1024 + 32);
    }
    else if (DRV_IS_TMG(lchip))
    {
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_coupleNumber_f, &fib_acc_ctl, 0);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_nonCoupleNumber_f, &fib_acc_ctl, 32);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_unusedNumber_f, &fib_acc_ctl, 64);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_coupleNumber_f, &fib_acc_ctl, 0);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_nonCoupleNumber_f, &fib_acc_ctl, 32);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_unusedNumber_f, &fib_acc_ctl, 64);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_coupleNumber_f, &fib_acc_ctl, 32);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_nonCoupleNumber_f, &fib_acc_ctl, 64);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_unusedNumber_f, &fib_acc_ctl, 96);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_coupleNumber_f, &fib_acc_ctl, 32);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_nonCoupleNumber_f, &fib_acc_ctl, 64);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_unusedNumber_f, &fib_acc_ctl, 96);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_coupleNumber_f, &fib_acc_ctl, 32);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_nonCoupleNumber_f, &fib_acc_ctl, 64);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_unusedNumber_f, &fib_acc_ctl, 96);

        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_5_coupleNumber_f, &fib_acc_ctl, 64);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_5_nonCoupleNumber_f, &fib_acc_ctl, 96);
        SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_5_unusedNumber_f, &fib_acc_ctl, 128);

        SetFibAccelerationCtl(V, agingPtrDemarcation0_f, &fib_acc_ctl, 64   * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation1_f, &fib_acc_ctl, 128  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation2_f, &fib_acc_ctl, 224  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation3_f, &fib_acc_ctl, 320  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation4_f, &fib_acc_ctl, 416  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation5_f, &fib_acc_ctl, 544  * 1024 + 32);
        SetFibAccelerationCtl(V, agingPtrDemarcation6_f, &fib_acc_ctl, 672  * 1024 + 32);
    }
    cmd = DRV_IOW(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_acc_ctl));

    cmd = DRV_IOR(NeoLpmCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &neo_Lpm_ctl));

    /* AgingIndexBase must include cam index but should not include tcam index according to specification */
    for (loop = 0; loop < 5; loop++)
    {
        value = DRV_IS_TMG(lchip) ? (agingPtr_arr1[loop] * 1024 + 32) : (agingPtr_arr[loop] * 1024 + 32);
        DRV_IOW_FIELD(lchip, NeoLpmCtl_t, NeoLpmCtl_group0Memory0AgingIndexBase_f + loop, &value, &neo_Lpm_ctl);
    }

    for (loop = 0; loop < 5; loop++)
    {
        value = DRV_IS_TMG(lchip) ? (agingPtr_arr1[loop + 5] * 1024 + 32) : (agingPtr_arr[loop + 5] * 1024 + 32);
        DRV_IOW_FIELD(lchip, NeoLpmCtl_t, NeoLpmCtl_group1Memory0AgingIndexBase_f + loop, &value, &neo_Lpm_ctl);
    }

    cmd = DRV_IOW(NeoLpmCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &neo_Lpm_ctl));

    cmd = DRV_IOR(DynamicFibKeyDsAgingAntFlowIndexCam_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &antflow_age_cam));
    if (DRV_IS_TMM(lchip))
    {
        if (GetDynamicFibKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable0_f, &antflow_age_cam)
            && GetDynamicFibKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable1_f, &antflow_age_cam))
        {
            /* memory 103 and memory 104 */
            min_ptr = 32 * 1024 + 32 + 32 * 1024 * 2 + 192 * 1024 * 3;
            max_ptr = 32 * 1024 + 32 + 32 * 1024 * 2 + 192 * 1024 * 3 + 256 * 1024 * 2 - 1;
        }
        else if (GetDynamicFibKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable0_f, &antflow_age_cam))
        {
            /* memory 103 */
            min_ptr = 32 * 1024 + 32 + 32 * 1024 * 2 + 192 * 1024 * 3;
            max_ptr = 32 * 1024 + 32 + 32 * 1024 * 2 + 192 * 1024 * 3 + 256 * 1024 - 1;
        }
        else if (GetDynamicFibKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable1_f, &antflow_age_cam))
        {
            /* memory 104 */
            min_ptr = 32 * 1024 + 32 + 32 * 1024 * 2 + 192 * 1024 * 3 + 256 * 1024;
            max_ptr = 32 * 1024 + 32 + 32 * 1024 * 2 + 192 * 1024 * 3 + 256 * 1024 * 2 - 1;
        }
    }
    else if (DRV_IS_TMG(lchip))
    {
        if (GetDynamicFibKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable0_f, &antflow_age_cam)
        && GetDynamicFibKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable1_f, &antflow_age_cam))
        {
            /* memory 103 and memory 104 */
            min_ptr = 16 * 1024 + 32 + 64 * 1024 * 2 + 96 * 1024 * 3;
            max_ptr = 16 * 1024 + 32 + 64 * 1024 * 2 + 96 * 1024 * 3 + 128 * 1024 * 2 - 1;
        }
        else if (GetDynamicFibKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable0_f, &antflow_age_cam))
        {
            /* memory 103 */
            min_ptr = 16 * 1024 + 32 + 64 * 1024 * 2 + 96 * 1024 * 3;
            max_ptr = 16 * 1024 + 32 + 64 * 1024 * 2 + 96 * 1024 * 3 + 128 * 1024 - 1;
        }
        else if (GetDynamicFibKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable1_f, &antflow_age_cam))
        {
            /* memory 104 */
            min_ptr = 16 * 1024 + 32 + 64 * 1024 * 2 + 96 * 1024 * 3 + 128 * 1024;
            max_ptr = 16 * 1024 + 32 + 64 * 1024 * 2 + 96 * 1024 * 3 + 128 * 1024 * 2 - 1;
        }
    }

    cmd = DRV_IOR(IpeAgingCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aging_ctl));

    SetIpeAgingCtl(V, antFlowAgingMinPtr_f, &ipe_aging_ctl, min_ptr);/* need include tcam aging ptr according to specification */
    SetIpeAgingCtl(V, antFlowAgingMaxPtr_f, &ipe_aging_ctl, max_ptr);

    cmd = DRV_IOW(IpeAgingCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aging_ctl));

    value = min_ptr;/* need include tcam aging ptr according to specification */
    cmd = DRV_IOW(AntFlowCtl_t, AntFlowCtl_antFlowAgingMinPtr_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOR(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host0_lookup_ctl));
    value = DRV_IS_TMM(lchip)? (1152 * 1024 + 32):(672 * 1024 + 32);
    SetFibHost0HashLookupCtl(V, fibHost0L3Level0AgingIndexBase_f, &host0_lookup_ctl, value);
    SetFibHost0HashLookupCtl(V, fibHost0L3Level1AgingIndexBase_f, &host0_lookup_ctl, (value + (DRV_IS_TMM(lchip) ? 16 * 1024 : 32 * 1024)));
    SetFibHost0HashLookupCtl(V, fibHost0IpCamLookupAgingIndexBase_f, &host0_lookup_ctl, (value + (DRV_IS_TMM(lchip) ? 32 * 1024 : 64 * 1024)));
    cmd = DRV_IOW(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host0_lookup_ctl));


    cmd = DRV_IOR(FibHost1HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host1_lookup_ctl));

    value = DRV_IS_TMM(lchip) ? (1152 * 1024 + 32 * 1024 + 32 + 32 + 32) : (672 * 1024 + 64 * 1024 + 32 + 32 + 32);

    SetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &host1_lookup_ctl, value);
    SetFibHost1HashLookupCtl(V, fibHost1Level1AgingIndexBase_f, &host1_lookup_ctl, 8 * 1024);
    SetFibHost1HashLookupCtl(V, fibHost1Level2AgingIndexBase_f, &host1_lookup_ctl, 16 * 1024);
    SetFibHost1HashLookupCtl(V, fibHost1Level3AgingIndexBase_f, &host1_lookup_ctl, 24 * 1024);

    cmd = DRV_IOW(FibHost1HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host1_lookup_ctl));


    sys_usw_ftm_get_srv_aging_base(lchip, 0, &aging_base);

    cmd = DRV_IOR(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_engine_ctl));
    /* Ant Flow always use couple mode */
    SetLagEngineCtl(V, antFlowAgingBase_f, &lag_engine_ctl, aging_base);/* include cam but but not tcam */
    SetLagEngineCtl(V, antFlowAgingMode_f, &lag_engine_ctl, 1);/* Hw Aging */
    SetLagEngineCtl(V, antFlowAgingTimer_f, &lag_engine_ctl, SYS_AGING_TIMER_INDEX_RSV);
    cmd = DRV_IOW(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_engine_ctl));

    sys_usw_ftm_get_srv_aging_base(lchip, 1, &aging_base);
    cmd = DRV_IOR(IpeEcmpCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_ecmp_ctl));
     /* Ant Flow always use couple mode */
    SetIpeEcmpCtl(V, antFlowAgingBase_f, &ipe_ecmp_ctl, aging_base);/* include cam but but not tcam */
    SetIpeEcmpCtl(V, antFlowAgingMode_f, &ipe_ecmp_ctl, 1);/* Hw Aging */
    SetIpeEcmpCtl(V, antFlowAgingTimer_f, &ipe_ecmp_ctl, SYS_AGING_TIMER_INDEX_RSV);
    cmd = DRV_IOW(IpeEcmpCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_ecmp_ctl));

    /* set dma callback for learning & aging module */
    CTC_ERROR_RETURN(sys_usw_dma_register_cb(lchip, SYS_DMA_CB_TYPE_LERNING, sys_tmm_learning_aging_sync_data));

    return CTC_E_NONE;
}
STATIC int32
_sys_tmm_aging_get_level_free_agingptr(uint8 lchip, uint32* p_level_free_index)
{
    sal_memcpy(p_level_free_index, p_usw_la_master[lchip]->fib_free_ptr, sizeof(p_usw_la_master[lchip]->fib_free_ptr));
    return CTC_E_NONE;
}

int32
sys_tmm_aging_get_key_index(uint8 lchip, uint32 aging_ptr, uint8* domain_type, uint32* key_index)
{
    uint8 is_cam = 0;
    uint8 type = 0;
    uint8 current_level = 0;
    uint32 cmd = 0;
    uint32 aging_idx = 0;
    uint32 tcam_aging_num = 0;
    uint32 level_free_index[SYS_AGING_MAX_LEVEL] = {0};
    FibHost0HashLookupCtl_m hash_lookup_ctl;
    FibHost1HashLookupCtl_m host1_lookup_ctl;

    if(DRV_FROM_AT(lchip))
    {
        return CTC_E_NOT_SUPPORT;/*sys cli, for debug show, no use*/
    }

    cmd = DRV_IOR(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &hash_lookup_ctl));

    cmd = DRV_IOR(FibHost1HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host1_lookup_ctl));

    sys_usw_ftm_query_table_entry_num(lchip, DsAgingStatusTcam_t, &tcam_aging_num);
    tcam_aging_num = tcam_aging_num * 32;

    /* for TsingMa.MX */
    if (aging_ptr < tcam_aging_num)
    {
        uint32 entry_num = 0;
        CTC_ERROR_RETURN(sys_usw_ftm_query_table_entry_num(lchip, DsLpmTcamIpv4HalfKey_t, &entry_num));
        /*Tcam or Tcam Nat aging*/
        if (aging_ptr >= entry_num)
        {
            *domain_type = SYS_AGING_DOMAIN_NAT_TCAM;
            *key_index   = (aging_ptr - entry_num) / 4;
        }
        else
        {
            *domain_type = SYS_AGING_DOMAIN_TCAM;
            *key_index   = aging_ptr;
        }
    }
    else
    {
        aging_idx = aging_ptr - tcam_aging_num;
        CTC_ERROR_RETURN(_sys_tmm_aging_get_mem_id(lchip, aging_idx, &is_cam, &type, &current_level));

        if (is_cam)
        {
            if (SYS_AGING_DOMAIN_MAC_HASH == type)
            {
                *key_index = aging_idx;
            }
            else if (SYS_AGING_DOMAIN_IP_HASH == type)
            {
                *key_index = aging_idx - GetFibHost0HashLookupCtl(V, fibHost0IpCamLookupAgingIndexBase_f, &hash_lookup_ctl);
            }
            else if (SYS_AGING_DOMAIN_HOST1 == type)
            {
                *key_index = aging_idx - GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &host1_lookup_ctl);
            }
            *domain_type = type;
        }
        else
        {
            uint8 loop = 0;
            uint8 mem_id_array[DRV_FTM_FTM_MAX_EDRAM_MEM_NUM] = {0};
            uint32 entry_num_array[DRV_FTM_FTM_MAX_EDRAM_MEM_NUM] = {0};
            uint32 sram_type = 0;

            CTC_ERROR_RETURN(sys_usw_ftm_get_edram_info(lchip, current_level, &sram_type, mem_id_array, entry_num_array));

            if (DRV_FTM_SRAM_TBL_MAC_HASH_KEY == sram_type)
            {
                /* for mac hash */
                *domain_type = SYS_AGING_DOMAIN_MAC_HASH;
                _sys_tmm_aging_get_level_free_agingptr(lchip, level_free_index);

                *key_index = aging_idx;
                for (loop = 0; loop < current_level; loop++)
                {
                    *key_index = *key_index - level_free_index[loop];
                }
            }
            else if ((DRV_FTM_SRAM_TBL_LPM_LKP_KEY0 == sram_type) || (DRV_FTM_SRAM_TBL_LPM_LKP_KEY1 == sram_type))
            {
                /* for lpm hash */
                uint8 loop = 0;
                uint8 loop1 = 0;
                uint8 lpm_memory_id = 0;
                uint8 lpm_hit_number = 0;
                uint32 snake_pointer = 0;
                uint32 total_entry_num = 0;
                uint32 group0_aging_base = 0;
                uint32 group1_aging_base = 0;
                NeoLpmCtl_m neo_lpm_ctl;

                cmd = DRV_IOR(NeoLpmCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &neo_lpm_ctl));

                if (current_level < 2)
                {
                    SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "[Aging]The aging ptr is invalid!\n");
                    return CTC_E_INVALID_PARAM;
                }

                lpm_memory_id = (current_level - 2);/* Maximum start from memory 0 to memory 4 regardless of allocation or not */
                DRV_IOR_FIELD(lchip, NeoLpmCtl_t, NeoLpmCtl_group1Memory0AgingIndexBase_f + lpm_memory_id, &group1_aging_base, &neo_lpm_ctl);
                if (aging_idx < group1_aging_base)
                {
                    /* lpm group 0 */
                    DRV_IOR_FIELD(lchip, NeoLpmCtl_t, NeoLpmCtl_group0Memory0AgingIndexBase_f + lpm_memory_id, &group0_aging_base, &neo_lpm_ctl);
                    snake_pointer = (aging_idx - group0_aging_base) / 6;
                    lpm_hit_number = (aging_idx - group0_aging_base) % 6;

                    *domain_type = SYS_AGING_DOMAIN_LPM_HASH_GROUP0;
                }
                else
                {
                    /* lpm group 1 */
                    snake_pointer = (aging_idx - group1_aging_base) / 6;
                    lpm_hit_number = (aging_idx - group1_aging_base) % 6;

                    *domain_type = SYS_AGING_DOMAIN_LPM_HASH_GROUP1;
                }

                /* Get memory allocate situation from FTM */
                for (loop = 0; loop < DRV_FTM_FTM_MAX_EDRAM_MEM_NUM; loop++)
                {
                    /* all memories are sorted in order */
                    if (mem_id_array[loop] == current_level)
                    {
                        for (loop1 = 0; loop1 < loop; loop1++)
                        {
                            total_entry_num += entry_num_array[loop1];
                        }
                        break;
                    }
                }

                *key_index = ((lpm_hit_number << 24) & 0xFF000000) | ((snake_pointer + total_entry_num) & 0x00FFFFFF);
            }
            else if (DRV_FTM_SRAM_TBL_FIB0_HASH_KEY == sram_type)
            {
                /* for host0 ip hash */
                if (aging_idx < GetFibHost0HashLookupCtl(V, fibHost0L3Level1AgingIndexBase_f, &hash_lookup_ctl))
                {
                    *key_index = aging_idx - GetFibHost0HashLookupCtl(V, fibHost0L3Level0AgingIndexBase_f, &hash_lookup_ctl) + 32;
                }
                else
                {
                    *key_index = aging_idx - GetFibHost0HashLookupCtl(V, fibHost0L3Level1AgingIndexBase_f, &hash_lookup_ctl)
                    + GetFibHost0HashLookupCtl(V, fibHost0L3Level1IndexBase_f, &hash_lookup_ctl) + 32;
                }

                *domain_type = SYS_AGING_DOMAIN_IP_HASH;
            }
            else if (DRV_FTM_SRAM_TBL_FIB1_HASH_KEY == sram_type)
            {
                uint8 step = FibHost1HashLookupCtl_fibHost1Level2AgingIndexBase_f - FibHost1HashLookupCtl_fibHost1Level1AgingIndexBase_f;
                if (current_level == 14)
                {
                    *key_index = aging_idx - GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &host1_lookup_ctl);
                }
                else
                {
                    *key_index = aging_idx - GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &host1_lookup_ctl)
                    - GetFibHost1HashLookupCtl(V, fibHost1Level1AgingIndexBase_f + step * (current_level - 15), &host1_lookup_ctl)
                    + GetFibHost1HashLookupCtl(V, fibHost1Level1IndexBase_f + step * (current_level - 15), &host1_lookup_ctl);
                }
                *domain_type = SYS_AGING_DOMAIN_HOST1;
            }
        }
    }

    return CTC_E_NONE;
}

int32
sys_tmm_aging_get_hash_aging_ptr(uint8 lchip, uint8 domain_type, uint32 key_index, uint32* aging_ptr)
{
    uint32* p_level = p_usw_la_master[lchip]->aging_base[domain_type].key_index_base;
    uint32* hash_enable = p_usw_la_master[lchip]->aging_base[domain_type].level_en;
    uint8 index = 0;
    uint8 find_flag=0;

    if(DRV_FROM_AT(lchip) && key_index >> 31)
    {
        /*bit31 means getting agingstatus from MacLearningCacheEntryValid*/
        *aging_ptr = key_index;
        return CTC_E_NONE;
    }

    /*1.Ptr located in Cam */
    if (key_index < 32)
    {
        *aging_ptr = key_index + p_usw_la_master[lchip]->aging_base[domain_type].cam_ptr_base;
        goto end;
    }

    /*2.Find key_index locate memory id*/
    for (index = 0; index < 7; index++)
    {
        if (hash_enable[index] && key_index < p_level[index + 1])
        {
            find_flag = 1;
            break;
        }
    }

    if (!find_flag)
    {
        SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "[Aging]The key-index is out of range! ");
        return CTC_E_INVALID_PARAM;
    }

    /*3.AgingPtr is aging base add the diff of key_index and its base*/
    *aging_ptr = p_usw_la_master[lchip]->aging_base[domain_type].aging_ptr_base[index] 
    + (key_index - p_usw_la_master[lchip]->aging_base[domain_type].key_index_base[index]);

end:
     /*4.Add Tcam aging num*/
     *aging_ptr +=p_usw_la_master[lchip]->aging_tcam_num;

    return CTC_E_NONE;
}

int32
sys_tmm_aging_get_lpm_aging_ptr(uint8 lchip, uint8 domain_type, uint32 key_index, uint32* aging_ptr)
{
    uint8 is_group0 = 0;
    uint8 mem_count = 0;
    uint8 memory_id = 0;
    uint8 lpm_memory_id = 0;
    uint32 snake_pointer = 0;
    uint32 local_aging_ptr = 0;
    uint32 hw_idx = 0;
    uint8 mem_en = 0;
    uint8 i=0,find_flag=0;
    uint8 level = (key_index >> 30) & 0x1;
    uint8 hw_position = ((key_index >> 24) & 0x3F);
    uint32 snake_num_per_memory = level? (16 * 1024) : (8 * 1024);
    drv_ftm_info_detail_t ftm_info;
    sys_aging_base_t *p_aging_base = &p_usw_la_master[lchip]->aging_base[SYS_AGING_DOMAIN_LPM_HASH_GROUP0];
    sys_aging_base_t *p_aging_base_1 = &p_usw_la_master[lchip]->aging_base[SYS_AGING_DOMAIN_LPM_HASH_GROUP1];
    
    uint32 aging_base[2][4]={{p_aging_base->aging_ptr_base[5],p_aging_base->aging_ptr_base[6]},{p_aging_base->aging_ptr_base[0],p_aging_base->aging_ptr_base[1],
        p_aging_base->aging_ptr_base[2],p_aging_base->aging_ptr_base[3]}};

    if (DRV_FROM_AT(lchip))
    {
        mem_en = level? p_aging_base->level_en[0] : p_aging_base->level_en[1];
        hw_idx = (key_index & (0x00FFFFFF));
        snake_pointer = hw_idx % snake_num_per_memory;
        memory_id = hw_idx / snake_num_per_memory;
        if (SYS_AGING_DOMAIN_LPM_HASH_GROUP1 == domain_type)
        {
            snake_pointer += snake_num_per_memory;
        }
        local_aging_ptr = hw_position + ((snake_pointer << 1) + (snake_pointer << 2));

        for (i = 0; i < 4; i++)
        {
            if (CTC_IS_BIT_SET(mem_en, i) && (memory_id == i))
            {
                find_flag = 1;
                break;
            }
        }

        if (!find_flag)
        {
            SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "[Aging]The key-index is out of range! ");
            return CTC_E_INVALID_PARAM;
        }
        *aging_ptr = aging_base[level][i] + local_aging_ptr;
    }
    else
    {
        sal_memset(&ftm_info, 0, sizeof(drv_ftm_info_detail_t));
        is_group0 = (SYS_AGING_DOMAIN_LPM_HASH_GROUP0 == domain_type) ? 1 : 0;
    
        mem_count = (key_index & (0x00FFFFFF)) / (16 * 1024);/* means how many memory blocks already be allocated before the current memory which the keyindex located in, thus can not be last memory */
        snake_pointer = (key_index & (0x00FFFFFF)) % (16 * 1024);
        local_aging_ptr = ((key_index >> 24) & 0xFF) + (snake_pointer << 1) + (snake_pointer << 2);/* snake_pointer * 6 */
    
        /* need achieve memory_id start from 0 to 4 regardless of allocation or not */
        ftm_info.info_type = DRV_FTM_INFO_TYPE_EDRAM;
        ftm_info.tbl_type = is_group0 ? DRV_FTM_SRAM_TBL_LPM_LKP_KEY0 : DRV_FTM_SRAM_TBL_LPM_LKP_KEY1;
        drv_usw_ftm_get_info_detail(lchip, &ftm_info);
        if (mem_count >= ftm_info.tbl_entry_num)
        {
            return CTC_E_INVALID_PARAM;
        }
    
        /* The Memory which the key_index located in and its ID is addressed by FTM in uniform*/
        memory_id = ftm_info.mem_id[mem_count];
        lpm_memory_id = memory_id - 2;
        *aging_ptr = (is_group0? p_aging_base->aging_ptr_base[lpm_memory_id] : p_aging_base_1->aging_ptr_base[lpm_memory_id]) + local_aging_ptr;/* include cam but not include tcam */
    }
    *aging_ptr +=p_usw_la_master[lchip]->aging_tcam_num;
    return CTC_E_NONE;

}

int32
sys_tmm_aging_set_aging_status(uint8 lchip, uint8 domain_type, uint32 key_index, uint8 timer, uint8 status)
{
    int32 ret = CTC_E_NONE;
    drv_acc_in_t in;
    drv_acc_out_t out;
    uint32 aging_tcam_base = 0;
    uint32 aging_ptr = 0;
    uint32 cmd = 0;
    uint32 status_tbl =0;
    uint32 value = 0;
    uint8 use_aging_ptr = 0;
    uint8 pp_en = CTC_IS_BIT_SET(domain_type, SYS_AGING_PP_EN_BIT);
    uint8 step = 0;

    CTC_BIT_UNSET(domain_type, SYS_AGING_PP_EN_BIT); 
    sal_memset(&in, 0, sizeof(drv_acc_in_t));
    sal_memset(&out, 0, sizeof(drv_acc_out_t));

    use_aging_ptr = (domain_type == SYS_AGING_DOMAIN_MAC_HASH)? 0 : 1;
    CTC_ERROR_RETURN(sys_usw_ftm_query_table_entry_num(lchip, DsAgingStatusTcam_t, &aging_tcam_base));
    aging_tcam_base = aging_tcam_base * 32;

    if(use_aging_ptr)
    {
        if (MCHIP_LA(lchip)->get_aging_ptr)
        {
            CTC_ERROR_RETURN(MCHIP_LA(lchip)->get_aging_ptr(lchip, domain_type, key_index, &aging_ptr));
        }
        CTC_BIT_SET(in.flag, DRV_ACC_AGING_EN);
    }

    sal_mutex_lock(p_usw_la_master[lchip]->p_aging_mutex);

    if(!pp_en)
    {
        in.type = DRV_ACC_TYPE_UPDATE;
        in.op_type = DRV_ACC_OP_BY_INDEX;
        if (domain_type == SYS_AGING_DOMAIN_TCAM || domain_type == SYS_AGING_DOMAIN_NAT_TCAM)
        {
            in.index = aging_ptr;
            in.value = 1;/* value 1 means update Tcam aging Status */
        }
        else
        {
            in.index = use_aging_ptr? (aging_ptr - aging_tcam_base) : key_index;
        }
        in.timer_index = timer;
        in.data = &status;
        in.tbl_id = DsAging_t;
        in.module= DRV_ACC_HASH_MODULE_AGING;
        ret = drv_acc_api(lchip, &in, &out);
    }
    else if(DRV_FROM_AT(lchip))
    {
        value = status;
        status_tbl = ((SYS_AGING_DOMAIN_TCAM == domain_type) || (SYS_AGING_DOMAIN_NAT_TCAM == domain_type)) ? DsAgingStatusTcam_t : DsAgingStatusFib_t;
        aging_ptr = ((SYS_AGING_DOMAIN_TCAM == domain_type) || (SYS_AGING_DOMAIN_NAT_TCAM == domain_type)) ? aging_ptr : (aging_ptr - aging_tcam_base);
        step = DsAgingStatus_array_1_agingStatus_f - DsAgingStatus_array_0_agingStatus_f;
        cmd = DRV_IOW(status_tbl, DsAgingStatus_array_0_agingStatus_f + (aging_ptr % 32)*step);
        DRV_FIELD_IOCTL(lchip, aging_ptr >> 5, DRV_CMD_PP_EN(cmd), &value);
    }
    sal_mutex_unlock(p_usw_la_master[lchip]->p_aging_mutex);

    return ret;
}

int32
sys_tmm_aging_get_aging_status(uint8 lchip, uint8 domain_type, uint32 key_index, uint8* hit)
{
    CTC_ERROR_RETURN(sys_usw_aging_get_aging_status(lchip, domain_type, key_index, hit));
    return CTC_E_NONE;
}

int32
sys_tmm_aging_get_aging_timer(uint8 lchip, uint8 domain_type, uint32 key_index, uint8* p_timer)
{
    CTC_ERROR_RETURN(sys_usw_aging_get_aging_timer(lchip, domain_type, key_index, p_timer));
    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_learning_aging_decode_leaning_data(uint8 lchip, void* p_info, ctc_learning_cache_entry_t* p_entry)
{
    sys_learning_aging_decode_tmm_t* p_learning = (sys_learning_aging_decode_tmm_t*)p_info;
    hw_mac_addr_t             mac_sa   = { 0 };

    mac_sa[0] = p_learning->macsa_0_20 | ((p_learning->macsa_21_47 & 0x7FF) << 21);
    mac_sa[1] = (p_learning->macsa_21_47 >> 11) & 0xFFFF;
    SYS_USW_SET_USER_MAC(p_entry->mac, mac_sa);
    p_entry->fid                = (p_learning->vsi_id_5_14 << 5) | p_learning->vsi_id_0_4;

    if (!p_learning->is_global_src_port)
    {
        p_entry->logic_port = p_learning->learning_source_port;
        p_entry->is_logic_port = 1;
    }
    else
    {
        p_entry->is_logic_port = 0;
        p_entry->global_src_port = SYS_MAP_DRV_GPORT_TO_CTC_GPORT(p_learning->learning_source_port);
    }

    p_entry->cvlan_id = (p_learning->uShare_9_40 >> 15)&0xFFF;
    p_entry->svlan_id = ((p_learning->uShare_9_40 >> 27) & 0x1F) | ((p_learning->uShare_41_51 & 0x7F) << 5);

    p_entry->ether_oam_md_level = (p_learning->uShare_41_51 >> 7) & 0x7;
    p_entry->is_ether_oam       = (p_learning->uShare_41_51 >> 10) & 0x1;

    p_entry->mac_sa_0to31 = (p_entry->mac[5] | (p_entry->mac[4] << 8) |
        (p_entry->mac[3] << 16) | (p_entry->mac[2] << 24));
    p_entry->mac_sa_32to47 = (p_entry->mac[1] | (p_entry->mac[0] << 8));
    p_entry->is_hw_sync = p_usw_la_master[lchip]->is_hw_sync;

    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_learning_aging_decode_aging_data(uint8 lchip, void* p_info, ctc_aging_info_entry_t* p_entry, uint8* is_ip)
{
    sys_learning_aging_decode_tmm_t* p_aging = (sys_learning_aging_decode_tmm_t*)p_info;
    uint8  hash_type = 0;
    uint32  dsmac_index = 0;
    DsMac_m dsmac;
    uint32 cmd = 0;

    hw_mac_addr_t             mac_sa   = { 0 };
    mac_addr_t mac_tmp;

    hash_type = (p_aging->uShare_9_40 >> 16) & 0x7;
    if (hash_type == DRV_ENUM(DRV_FIBHOST0PRIMARYHASHTYPE_MAC))
    {
        /*1.1 mac aging */
        mac_sa[0] = ((p_aging->macsa_21_47 & 0x7FF) << 21) | p_aging->macsa_0_20;
        mac_sa[1] = (p_aging->macsa_21_47 >> 11) & 0xFFFF;
        SYS_USW_SET_USER_MAC(p_entry->mac, mac_sa);
        p_entry->fid                = (p_aging->vsi_id_5_14 << 5) | p_aging->vsi_id_0_4;
        p_entry->is_hw_sync        = (p_aging->uShare_41_51 >> 10) & 0x1;
        p_entry->aging_type = CTC_AGING_TYPE_MAC;
        *is_ip = 0;

        dsmac_index   = p_aging->uShare_0_8 | ((p_aging->uShare_9_40 & 0x1FF) << 9);
        cmd = DRV_IOR(DsMac_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, dsmac_index, cmd, &dsmac));

        p_entry->is_logic_port = GetDsMac(V, learnSource_f, &dsmac);
        if (p_entry->is_logic_port)
        {
            p_entry->gport = GetDsMac(V, logicSrcPort_f, &dsmac);
        }
        else
        {
            p_entry->gport = SYS_MAP_DRV_GPORT_TO_CTC_GPORT(GetDsMac(V, globalSrcPort_f, &dsmac));
        }
    }
    else
    {
        SYS_USW_SET_USER_MAC(mac_tmp, mac_sa);
        SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Invalid Aging hash type:%d, mac: %.4x.%.4x.%.4x, fid:%d\n", hash_type,
                                   mac_tmp[0], mac_tmp[2], mac_tmp[4], GetDmaFibLearnFifo(V, vsiId_f, p_aging));

        /*Not support*/
        SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Feature not supported \n");
        return CTC_E_NOT_SUPPORT;
    }
    return CTC_E_NONE;
}

int32
sys_tmm_learning_aging_sync_data(uint8 lchip, void* p_info)
{
    uint32                     index    = 0;
    uint32                     i        = 0;
    sys_learning_aging_decode_tmm_t      * p_fifo = NULL;
    CpuInfoLearning_s * p_cpu_info = NULL;
    sys_learning_aging_decode_tmm_t* p_next_fifo = NULL;
    hw_mac_addr_t             mac_sa   = { 0 };
    uint8   is_aging = 0;
    uint8 is_ip_aging = 0;
    sys_dma_info_t* p_dma_info = NULL;
    uint8 gchip = 0;
    uint32 ad_idx = 0;
    CTC_INTERRUPT_EVENT_FUNC cb = NULL;
    CTC_INTERRUPT_EVENT_FUNC aging_cb = NULL;

    CTC_PTR_VALID_CHECK(p_info);
    CTC_PTR_VALID_CHECK(p_usw_la_master[lchip]);

    SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    p_usw_la_master[lchip]->ctc_learning.sync_mode = 1;
    p_usw_la_master[lchip]->ctc_aging.sync_mode = 1;

    p_dma_info = (sys_dma_info_t*)p_info;
    CTC_ERROR_RETURN(sys_usw_interrupt_get_event_cb(lchip, CTC_EVENT_L2_SW_LEARNING, &cb));
    CTC_ERROR_RETURN(sys_usw_interrupt_get_event_cb(lchip, CTC_EVENT_L2_SW_AGING, &aging_cb));
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));

    p_cpu_info = (CpuInfoLearning_s *) p_dma_info->p_data;

    for (i = 0; i < p_dma_info->entry_num; i++)
    {

        p_fifo = (sys_learning_aging_decode_tmm_t*)SYS_USW_DMA_GET_INFO_ADDR(lchip, &p_cpu_info[i]);

        is_aging  = !p_fifo->is_learning;

        if (!is_aging)
        {
            _sys_tmm_learning_aging_decode_leaning_data(lchip, p_fifo, &(p_usw_la_master[lchip]->ctc_learning.learning_entry[index]));
            p_usw_la_master[lchip]->ctc_learning.entry_num = (++index);
        }
        else
        {
            if ((((p_fifo->uShare_9_40 >> 16) & 0x7) == DRV_ENUM(DRV_FIBHOST0PRIMARYHASHTYPE_MAC)) &&
                p_fifo->is_global_src_port)
            {
                /*for pending aging , sdk process direct , do not sync to sys*/
                p_usw_la_master[lchip]->l2_addr.fid = (p_fifo->vsi_id_5_14 << 5) | p_fifo->vsi_id_0_4;
                ad_idx = p_fifo->uShare_0_8 | ((p_fifo->uShare_9_40 & 0x1FF) << 9);

                mac_sa[0] = p_fifo->macsa_0_20 | ((p_fifo->macsa_21_47 & 0x7FF) << 21);
                mac_sa[1] = (p_fifo->macsa_21_47 >> 11) & 0xFFFF;
                SYS_USW_SET_USER_MAC(p_usw_la_master[lchip]->l2_addr.mac, mac_sa);
                CTC_ERROR_RETURN(sys_usw_l2_remove_pending_fdb(lchip, &p_usw_la_master[lchip]->l2_addr, ad_idx));
            }
            else
            {
                _sys_tmm_learning_aging_decode_aging_data(lchip, p_fifo, &(p_usw_la_master[lchip]->ctc_aging.aging_entry[index]), &is_ip_aging);
                p_usw_la_master[lchip]->ctc_aging.fifo_idx_num = (++index);
            }

        }

        p_next_fifo  = ((i + 1) == p_dma_info->entry_num) ? NULL :  (sys_learning_aging_decode_tmm_t*)SYS_USW_DMA_GET_INFO_ADDR(lchip, &p_cpu_info[i + 1]);

        if(!p_next_fifo || (is_aging != !p_next_fifo->is_learning)
            || ((aging_cb && (CTC_LEARNING_CACHE_MAX_INDEX == p_usw_la_master[lchip]->ctc_aging.fifo_idx_num)))
            || (cb && (CTC_LEARNING_CACHE_MAX_INDEX == p_usw_la_master[lchip]->ctc_learning.entry_num)))
        {
            if (p_learning_cb_mutex)
            {
                sal_mutex_lock(p_learning_cb_mutex);
            }

            if(aging_cb && p_usw_la_master[lchip]->ctc_aging.fifo_idx_num)
            {
                aging_cb(gchip, &p_usw_la_master[lchip]->ctc_aging);
                p_usw_la_master[lchip]->ctc_aging.fifo_idx_num = 0;
            }
            else if(cb && p_usw_la_master[lchip]->ctc_learning.entry_num)
            {
                cb(gchip, &p_usw_la_master[lchip]->ctc_learning);
                p_usw_la_master[lchip]->ctc_learning.entry_num = 0;
            }
            index = 0;

            if (p_learning_cb_mutex)
            {
                sal_mutex_unlock(p_learning_cb_mutex);
            }
        }
    }

    return CTC_E_NONE;
}

#define __ARCTIC_FUNCTION___

#if defined(ARCTIC)
STATIC int32
_sys_at_learning_aging_decode_leaning_data(uint8 lchip, void* p_info, ctc_learning_cache_entry_t* p_entry)
{
    sys_at_learning_aging_decode_t* p_learning = (sys_at_learning_aging_decode_t*)p_info;
    hw_mac_addr_t             mac_sa   = { 0 };

    mac_sa[0] = p_learning->u1.learning.mac_25_0 | ((p_learning->u1.learning.mac_47_26 & 0x3F) << 26);
    mac_sa[1] = (p_learning->u1.learning.mac_47_26 >> 6) & 0xFFFF;
    SYS_USW_SET_USER_MAC(p_entry->mac, mac_sa);

    p_entry->fid = p_learning->vsiId_8_0 | (p_learning->u1.learning.vsiId_14_9 << 9);

    if (!p_learning->u1.learning.isGlobalSrcPort)
    {
        p_entry->logic_port = p_learning->u1.learning.learningSourcePort_8_0 | (p_learning->u1.learning.learningSourcePort_15_9 << 9);
        p_entry->is_logic_port = 1;
    }
    else
    {
        p_entry->is_logic_port = 0;
        p_entry->global_src_port = SYS_MAP_DRV_GPORT_TO_CTC_GPORT(p_learning->u1.learning.learningSourcePort_8_0 | (p_learning->u1.learning.learningSourcePort_15_9 << 9));
    }

    p_entry->cvlan_id = p_learning->u1.learning.oldCvlanId;
    p_entry->svlan_id = p_learning->u1.learning.oldSvlanId;

    p_entry->ether_oam_md_level = p_learning->u1.learning.etherOamLevel_1_0 | (p_learning->u1.learning.etherOamLevel_2_2 << 2);
    p_entry->is_ether_oam       = p_learning->u1.learning.isEtherOam;

    p_entry->mac_sa_0to31 = (p_entry->mac[5] | (p_entry->mac[4] << 8) |
        (p_entry->mac[3] << 16) | (p_entry->mac[2] << 24));
    p_entry->mac_sa_32to47 = (p_entry->mac[1] | (p_entry->mac[0] << 8));
    p_entry->is_hw_sync = p_usw_la_master[lchip]->is_hw_sync;

    return CTC_E_NONE;
}

STATIC int32
_sys_at_learning_aging_decode_aging_data(uint8 lchip, void* p_info, ctc_aging_info_entry_t* p_entry, uint8* is_ip)
{
    sys_at_learning_aging_decode_t* p_aging = (sys_at_learning_aging_decode_t*)p_info;
    uint8   hash_type = 0;
    uint32  dsmac_index = 0;
    DsMac_m dsmac;
    uint32 cmd = 0;

    hw_mac_addr_t             mac_sa   = { 0 };

    hash_type = p_aging->u1.aging.hashType;

    if (hash_type == DRV_ENUM(DRV_FIBHOST0PRIMARYHASHTYPE_MAC))
    {
        /*1.1 mac aging */
        mac_sa[0] = (p_aging->u1.aging.mac_25_0) | (((p_aging->u1.aging.mac_47_26) & 0x3F) << 26);
        mac_sa[1] = ((p_aging->u1.aging.mac_47_26) >> 6) & 0xFFFF;
        SYS_USW_SET_USER_MAC(p_entry->mac, mac_sa);
        p_entry->fid                = (p_aging->u1.aging.vsiId_14_9 << 9) | p_aging->vsiId_8_0;
        p_entry->is_hw_sync        = p_aging->u1.aging.hwAging;
        p_entry->aging_type = CTC_AGING_TYPE_MAC;
        *is_ip = 0;

        dsmac_index   = (p_aging->u1.aging.dsAdIndex_17_9 << 9) | p_aging->u1.aging.dsAdIndex_8_0;
        cmd = DRV_IOR(DsMac_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, dsmac_index, cmd, &dsmac));

        p_entry->is_logic_port = GetDsMac(V, learnSource_f, &dsmac);
        if (p_entry->is_logic_port)
        {
            p_entry->gport = GetDsMac(V, logicSrcPort_f, &dsmac);
        }
        else
        {
            p_entry->gport = SYS_MAP_DRV_GPORT_TO_CTC_GPORT(GetDsMac(V, globalSrcPort_f, &dsmac));
        }
    }
    else
    {
        /*Not support*/
        SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Feature not supported \n");
        return CTC_E_NOT_SUPPORT;

    }
    return CTC_E_NONE;
}


int32
sys_at_learning_aging_sync_data(uint8 lchip, void* p_info)
{
    uint32                     index    = 0;
    uint32                     i        = 0;
    sys_at_learning_aging_decode_t      * p_fifo = NULL;
    CpuInfoLearning_m * p_cpu_info = NULL;
    sys_at_learning_aging_decode_t* p_next_fifo = NULL;
    hw_mac_addr_t             mac_sa   = { 0 };
    uint8   is_aging = 0;
    uint8 is_ip_aging = 0;
    sys_dma_info_t* p_dma_info = NULL;
    uint8 gchip = 0;
    uint32 ad_idx = 0;
    CTC_INTERRUPT_EVENT_FUNC cb = NULL;
    CTC_INTERRUPT_EVENT_FUNC aging_cb = NULL;

    CTC_PTR_VALID_CHECK(p_info);
    CTC_PTR_VALID_CHECK(p_usw_la_master[lchip]);

    SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    p_usw_la_master[lchip]->ctc_learning.sync_mode = 1;
    p_usw_la_master[lchip]->ctc_aging.sync_mode = 1;

    p_dma_info = (sys_dma_info_t*)p_info;
    CTC_ERROR_RETURN(sys_usw_interrupt_get_event_cb(lchip, CTC_EVENT_L2_SW_LEARNING, &cb));
    CTC_ERROR_RETURN(sys_usw_interrupt_get_event_cb(lchip, CTC_EVENT_L2_SW_AGING, &aging_cb));
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));

    p_cpu_info = (CpuInfoLearning_m *) p_dma_info->p_data;

    for (i = 0; i < p_dma_info->entry_num; i++)
    {

        SYS_LCHIP_CHECK_ACTIVE(lchip);

        p_fifo = (sys_at_learning_aging_decode_t*)SYS_USW_DMA_GET_INFO_ADDR(lchip, &p_cpu_info[i]);

        is_aging  = (p_fifo->shareType == 2);

        if (!is_aging)
        {
            _sys_at_learning_aging_decode_leaning_data(lchip, p_fifo, &(p_usw_la_master[lchip]->ctc_learning.learning_entry[index]));
            p_usw_la_master[lchip]->ctc_learning.entry_num = (++index);
        }
        else
        {

            if ((p_fifo->u1.aging.hashType == DRV_ENUM(DRV_FIBHOST0PRIMARYHASHTYPE_MAC)) && p_fifo->u1.aging.pending)
            {
                /*for pending aging , sdk process direct , do not sync to sys*/
                p_usw_la_master[lchip]->l2_addr.fid = (p_fifo->u1.aging.vsiId_14_9 << 9) | p_fifo->vsiId_8_0;
                ad_idx = (p_fifo->u1.aging.dsAdIndex_17_9 << 9) | p_fifo->u1.aging.dsAdIndex_8_0;

                mac_sa[0] = (p_fifo->u1.aging.mac_25_0) | (((p_fifo->u1.aging.mac_47_26) & 0x3F) << 26);
                mac_sa[1] = ((p_fifo->u1.aging.mac_47_26) >> 6) & 0xFFFF;
                SYS_USW_SET_USER_MAC(p_usw_la_master[lchip]->l2_addr.mac, mac_sa);
                CTC_ERROR_RETURN(sys_usw_l2_remove_pending_fdb(lchip, &p_usw_la_master[lchip]->l2_addr, ad_idx));
            }
            else
            {
                _sys_at_learning_aging_decode_aging_data(lchip, p_fifo, &(p_usw_la_master[lchip]->ctc_aging.aging_entry[index]), &is_ip_aging);
                p_usw_la_master[lchip]->ctc_aging.fifo_idx_num = (++index);
            }

        }

        p_next_fifo  = ((i + 1) == p_dma_info->entry_num) ? NULL :  (sys_at_learning_aging_decode_t*)SYS_USW_DMA_GET_INFO_ADDR(lchip, &p_cpu_info[i + 1]);

        if(!p_next_fifo || (is_aging != (p_next_fifo->shareType == 2))
            || ((aging_cb && (CTC_LEARNING_CACHE_MAX_INDEX == p_usw_la_master[lchip]->ctc_aging.fifo_idx_num)))
            || (cb && (CTC_LEARNING_CACHE_MAX_INDEX == p_usw_la_master[lchip]->ctc_learning.entry_num)))
        {
            if (p_learning_cb_mutex)
            {
                sal_mutex_lock(p_learning_cb_mutex);
            }

            if(aging_cb && p_usw_la_master[lchip]->ctc_aging.fifo_idx_num)
            {
                aging_cb(gchip, &p_usw_la_master[lchip]->ctc_aging);
                p_usw_la_master[lchip]->ctc_aging.fifo_idx_num = 0;
            }
            else if(cb && p_usw_la_master[lchip]->ctc_learning.entry_num)
            {
                cb(gchip, &p_usw_la_master[lchip]->ctc_learning);
                p_usw_la_master[lchip]->ctc_learning.entry_num = 0;
            }
            index = 0;

            if (p_learning_cb_mutex)
            {
                sal_mutex_unlock(p_learning_cb_mutex);
            }
        }
    }

    return CTC_E_NONE;
}


int32
sys_at_aging_set_register(uint8 lchip)
{

    uint32 cmd = 0;
    uint32 min_ptr = 0;
    uint32 max_ptr = 0;
    uint32 tmp_min_ptr = 0;
    FibAccelerationCtl_m fib_acc_ctl;
    NeoLpmCtl_m neo_Lpm_ctl;
    IpeAgingCtl_m ipe_aging_ctl;
    FibHost0HashLookupCtl_m host0_lookup_ctl;
    FibHost1HashLookupCtl_m host1_lookup_ctl;
    FlowHashLookupCtl_m flow_hash_lookup_ctl;
    DynamicFibKeyDsAgingAntFlowIndexCam_m antflow_age_cam;
    uint32 aging_base = 0;
    IpeEcmpCtl_m ipe_ecmp_ctl;
    LagEngineCtl_m lag_engine_ctl;
    PpAgingMode_m pp_aging_mode;
    ds1_t ds;
    uint8 dul_core_mode = (drv_vchip_get_core_num(lchip) > 1) ? 1 : 0;

    cmd = DRV_IOR(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_acc_ctl));

    sal_memset(ds, 0, sizeof(ds1_t));
    min_ptr = TCAM_AGING_NUM;
    max_ptr = min_ptr + 32;
    /*cam*/
    SetIpeAgingPointRangeCtl(V, g_0_maxPtr_f, &ds, max_ptr - 1);
    SetIpeAgingPointRangeCtl(V, g_0_minPtr_f, &ds, min_ptr);
    SetIpeAgingPointRangeCtl(V, g_0_isFdbRange_f, &ds, 1);
    SetIpeAgingPointRangeCtl(V, g_0_valid_f, &ds, 1);

    /*level 0*/
    if (GetFibAccelerationCtl(V, host0Level0MacHashEn_f, &fib_acc_ctl))
    {
        min_ptr = TCAM_AGING_NUM + 32;
        max_ptr = min_ptr + (32 * 1024);
        SetIpeAgingPointRangeCtl(V, g_1_maxPtr_f, &ds, max_ptr - 1);
        SetIpeAgingPointRangeCtl(V, g_1_minPtr_f, &ds, min_ptr);
        SetIpeAgingPointRangeCtl(V, g_1_isFdbRange_f, &ds, 1);
        SetIpeAgingPointRangeCtl(V, g_1_valid_f, &ds, 1);
    }
    /*level 1*/
    if (GetFibAccelerationCtl(V, host0Level1MacHashEn_f, &fib_acc_ctl))
    {
        min_ptr = TCAM_AGING_NUM + 32 + (32 * 1024);
        max_ptr = min_ptr + (32 * 1024);
        SetIpeAgingPointRangeCtl(V, g_2_maxPtr_f, &ds, max_ptr - 1);
        SetIpeAgingPointRangeCtl(V, g_2_minPtr_f, &ds, min_ptr);
        SetIpeAgingPointRangeCtl(V, g_2_isFdbRange_f, &ds, 1);
        SetIpeAgingPointRangeCtl(V, g_2_valid_f, &ds, 1);
    }
    /*level 2*/
    if (GetFibAccelerationCtl(V, host0Level2MacHashEn_f, &fib_acc_ctl))
    {
        min_ptr = TCAM_AGING_NUM + 32 + (64 * 1024);
        max_ptr = min_ptr + (96 * 1024);
        SetIpeAgingPointRangeCtl(V, g_3_maxPtr_f, &ds, max_ptr - 1);
        SetIpeAgingPointRangeCtl(V, g_3_minPtr_f, &ds, min_ptr);
        SetIpeAgingPointRangeCtl(V, g_3_isFdbRange_f, &ds, 1);
        SetIpeAgingPointRangeCtl(V, g_3_valid_f, &ds, 1);
    }
    /*level 3*/
    if (GetFibAccelerationCtl(V, host0Level3MacHashEn_f, &fib_acc_ctl))
    {
        min_ptr = TCAM_AGING_NUM + 32 + (160 * 1024);
        max_ptr = min_ptr + (96 * 1024);
        SetIpeAgingPointRangeCtl(V, g_4_maxPtr_f, &ds, max_ptr - 1);
        SetIpeAgingPointRangeCtl(V, g_4_minPtr_f, &ds, min_ptr);
        SetIpeAgingPointRangeCtl(V, g_4_isFdbRange_f, &ds, 1);
        SetIpeAgingPointRangeCtl(V, g_4_valid_f, &ds, 1);
    }
    /*level 4*/
    if (GetFibAccelerationCtl(V, host0Level4MacHashEn_f, &fib_acc_ctl))
    {
        min_ptr = TCAM_AGING_NUM + 32 + (256 * 1024);
        max_ptr = min_ptr + (192 * 1024);
        SetIpeAgingPointRangeCtl(V, g_5_maxPtr_f, &ds, max_ptr - 1);
        SetIpeAgingPointRangeCtl(V, g_5_minPtr_f, &ds, min_ptr);
        SetIpeAgingPointRangeCtl(V, g_5_isFdbRange_f, &ds, 1);
        SetIpeAgingPointRangeCtl(V, g_5_valid_f, &ds, 1);
    }
    /*level 5*/
    if (GetFibAccelerationCtl(V, host0Level5MacHashEn_f, &fib_acc_ctl))
    {
        min_ptr = TCAM_AGING_NUM + 32 + (448 * 1024);
        max_ptr = min_ptr + (192 * 1024);
        SetIpeAgingPointRangeCtl(V, g_6_maxPtr_f, &ds, max_ptr - 1);
        SetIpeAgingPointRangeCtl(V, g_6_minPtr_f, &ds, min_ptr);
        SetIpeAgingPointRangeCtl(V, g_6_isFdbRange_f, &ds, 1);
        SetIpeAgingPointRangeCtl(V, g_6_valid_f, &ds, 1);
    }
    cmd = DRV_IOW(IpeAgingPointRangeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));


    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_coupleNumber_f, &fib_acc_ctl, 0);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_nonCoupleNumber_f, &fib_acc_ctl, 16);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_0_unusedNumber_f, &fib_acc_ctl, 32);

    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_coupleNumber_f, &fib_acc_ctl, 0);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_nonCoupleNumber_f, &fib_acc_ctl, 16);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_1_unusedNumber_f, &fib_acc_ctl, 32);

    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_coupleNumber_f, &fib_acc_ctl, 32);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_nonCoupleNumber_f, &fib_acc_ctl, 64);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_2_unusedNumber_f, &fib_acc_ctl, 96);

    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_coupleNumber_f, &fib_acc_ctl, 32);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_nonCoupleNumber_f, &fib_acc_ctl, 64);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_3_unusedNumber_f, &fib_acc_ctl, 96);

    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_coupleNumber_f, &fib_acc_ctl, 64);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_nonCoupleNumber_f, &fib_acc_ctl, 128);
    SetFibAccelerationCtl(V, host0MaxFreeNumOnLevel_4_unusedNumber_f, &fib_acc_ctl, 192);


    SetFibAccelerationCtl(V, agingPtrDemarcation0_f, &fib_acc_ctl, 32   * 1024 + 32);
    SetFibAccelerationCtl(V, agingPtrDemarcation1_f, &fib_acc_ctl, 64   * 1024 + 32);
    SetFibAccelerationCtl(V, agingPtrDemarcation2_f, &fib_acc_ctl, 160  * 1024 + 32);
    SetFibAccelerationCtl(V, agingPtrDemarcation3_f, &fib_acc_ctl, 256  * 1024 + 32);
    SetFibAccelerationCtl(V, agingPtrDemarcation4_f, &fib_acc_ctl, 448  * 1024 + 32);
    SetFibAccelerationCtl(V, agingPtrDemarcation5_f, &fib_acc_ctl, 640  * 1024 + 32);
    SetFibAccelerationCtl(V, agingPtrDemarcation6_f, &fib_acc_ctl, 896 * 1024 + 32);
    SetFibAccelerationCtl(V, agingPtrDemarcation7_f, &fib_acc_ctl, 1152 * 1024 + 32);
    cmd = DRV_IOW(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &fib_acc_ctl));

    sal_memset(ds, 0, sizeof(ds1_t));
    cmd = DRV_IOR(DynamicKeyDsAgingAntFlowIndexCam_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &antflow_age_cam));
    tmp_min_ptr = 20 * 1024 + 32 + 32 * 1024 * 2 + 96 * 1024 * 2 + 192 * 1024 * 2;
    if (GetDynamicKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable0_f, &antflow_age_cam))
    {
        /* memory 104 */
        min_ptr = tmp_min_ptr;
        max_ptr = 20 * 1024 + 32 + 32 * 1024 * 2 + 96 * 1024 * 2 + 192 * 1024 * 2 + 256 * 1024 - 1;
        SetPpAgingPointRangeCtl(V, g_7_maxPtr_f, &ds, max_ptr);
        SetPpAgingPointRangeCtl(V, g_7_minPtr_f, &ds, min_ptr);
        SetPpAgingPointRangeCtl(V, g_7_agingMode_f, &ds, 1);
        SetPpAgingPointRangeCtl(V, g_7_valid_f, &ds, 1);
    }
    if (GetDynamicKeyDsAgingAntFlowIndexCam(V, dsAgingAntFlowCamEnable1_f, &antflow_age_cam))
    {
        /* memory 105 */
        min_ptr = 20 * 1024 + 32 + 32 * 1024 * 2 + 96 * 1024 * 2 + 192 * 1024 * 2 + 256 * 1024;
        max_ptr = 20 * 1024 + 32 + 32 * 1024 * 2 + 96 * 1024 * 2 + 192 * 1024 * 2 + 256 * 1024 * 2 - 1;
        SetPpAgingPointRangeCtl(V, g_8_maxPtr_f, &ds, max_ptr);
        SetPpAgingPointRangeCtl(V, g_8_minPtr_f, &ds, min_ptr);
        SetPpAgingPointRangeCtl(V, g_8_agingMode_f, &ds, 1);
        SetPpAgingPointRangeCtl(V, g_8_valid_f, &ds, 1);
    }
    cmd = DRV_IOW(PpAgingPointRangeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(IpeAgingCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aging_ctl));

    sal_memset(ds, 0, sizeof(ds1_t));
    cmd = DRV_IOR(PpAgingCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    SetPpAgingCtl(V, antFlowAgingMinPtr_f, &ds, tmp_min_ptr); /* need include tcam aging ptr according to specification */
    SetPpAgingCtl(V, antFlowAgingMaxPtr_f, &ds, max_ptr);
    SetIpeAgingCtl(V, dualCoreAgingMode_f, &ipe_aging_ctl, dul_core_mode ? 1 : 0);
    
    cmd = DRV_IOW(IpeAgingCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_aging_ctl));
    cmd = DRV_IOW(PpAgingCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    sal_memset(ds, 0, sizeof(ds1_t));
    SetAntFlowCtl(V, antFlowAgingMinPtr_f, &ds, tmp_min_ptr); /* need include tcam aging ptr according to specification */
    SetAntFlowCtl(V, maxTcamAgingNum_f, &ds, TCAM_AGING_NUM);
    cmd = DRV_IOW(AntFlowCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));


    /*lpm*/
    cmd = DRV_IOR(NeoLpmCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &neo_Lpm_ctl));
    /*level 0*/
    SetNeoLpmCtl(V, group0L0Memory0AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_100);
    SetNeoLpmCtl(V, group0L0Memory1AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_101);
    SetNeoLpmCtl(V, group1L0Memory0AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_100 + 48*1024);/*couple*/
    SetNeoLpmCtl(V, group1L0Memory1AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_101 + 48*1024);/*couple*/
    /*level 1*/
    SetNeoLpmCtl(V, group0Memory0AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_102);
    SetNeoLpmCtl(V, group0Memory1AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_103);
    SetNeoLpmCtl(V, group0Memory2AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_104);
    SetNeoLpmCtl(V, group0Memory3AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_105);
    SetNeoLpmCtl(V, group1Memory0AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_102 + 96*1024);/*couple*/
    SetNeoLpmCtl(V, group1Memory1AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_103 + 96*1024);/*couple*/
    SetNeoLpmCtl(V, group1Memory2AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_104 + 128*1024);/*couple*/
    SetNeoLpmCtl(V, group1Memory3AgingIndexBase_f, &neo_Lpm_ctl, SYS_AGIDX_BASE_MEMORY_105 + 128*1024);/*couple*/
    cmd = DRV_IOW(NeoLpmCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &neo_Lpm_ctl));

    /*host0(mac and ip)*/
    cmd = DRV_IOR(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host0_lookup_ctl));
    /*mac*/
    SetFibHost0HashLookupCtl(V, fibHost0L2Level_0_agingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_MEMORY_000 - 32);
    SetFibHost0HashLookupCtl(V, fibHost0L2Level_1_agingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_MEMORY_001 - 32);
    SetFibHost0HashLookupCtl(V, fibHost0L2Level_2_agingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_MEMORY_100 - 32);
    SetFibHost0HashLookupCtl(V, fibHost0L2Level_3_agingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_MEMORY_101 - 32);
    SetFibHost0HashLookupCtl(V, fibHost0L2Level_4_agingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_MEMORY_102 - 32);
    SetFibHost0HashLookupCtl(V, fibHost0L2Level_5_agingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_MEMORY_103 - 32);
    /*ip*/
    SetFibHost0HashLookupCtl(V, fibHost0L3Level_0_agingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_MEMORY_106);
    SetFibHost0HashLookupCtl(V, fibHost0L3Level_1_agingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_MEMORY_107);
    SetFibHost0HashLookupCtl(V, fibHost0IpCamLookupAgingIndexBase_f, &host0_lookup_ctl, SYS_AGIDX_BASE_HOST0_IP_CAM);
    cmd = DRV_IOW(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host0_lookup_ctl));

    /*host1*/
    cmd = DRV_IOR(FibHost1HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host1_lookup_ctl));
    SetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &host1_lookup_ctl, SYS_AGIDX_BASE_HOST1_CAM);
    SetFibHost1HashLookupCtl(V, fibHost1Level_0_agingIndexBase_f, &host1_lookup_ctl, 0);
    SetFibHost1HashLookupCtl(V, fibHost1Level_1_agingIndexBase_f, &host1_lookup_ctl, (16)*1024);
    SetFibHost1HashLookupCtl(V, fibHost1Level_2_agingIndexBase_f, &host1_lookup_ctl, (16 + 16)*1024);
    SetFibHost1HashLookupCtl(V, fibHost1Level_3_agingIndexBase_f, &host1_lookup_ctl, (16 + 16 + 8)*1024);
    SetFibHost1HashLookupCtl(V, fibHost1Level_4_agingIndexBase_f, &host1_lookup_ctl, (16 + 16 + 8 + 8)*1024);
    SetFibHost1HashLookupCtl(V, fibHost1Level_5_agingIndexBase_f, &host1_lookup_ctl, (16 + 16 + 8 + 8)*1024);

    SetFibHost1HashLookupCtl(V, fibHost1ExtAgingIndexOffset_f, &host1_lookup_ctl, SYS_AGIDX_BASE_MEMORY_104);
    SetFibHost1HashLookupCtl(V, fibHost1ExtLevel_0_agingIndexBase_f, &host1_lookup_ctl, 0);
    SetFibHost1HashLookupCtl(V, fibHost1ExtLevel_1_agingIndexBase_f, &host1_lookup_ctl, 256*1024);
    cmd = DRV_IOW(FibHost1HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &host1_lookup_ctl));

    /*flow hash*/
    cmd = DRV_IOR(FlowHashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &flow_hash_lookup_ctl));
    SetFlowHashLookupCtl(V, flowHashAgingIndexOffset_f, &flow_hash_lookup_ctl, SYS_AGIDX_BASE_MEMORY_100);
    SetFlowHashLookupCtl(V, flowHashLevel_0_agingIndexBase_f, &flow_hash_lookup_ctl, 0);
    SetFlowHashLookupCtl(V, flowHashLevel_1_agingIndexBase_f, &flow_hash_lookup_ctl, (96)*1024);
    SetFlowHashLookupCtl(V, flowHashLevel_2_agingIndexBase_f, &flow_hash_lookup_ctl, (96 + 96)*1024);
    SetFlowHashLookupCtl(V, flowHashLevel_3_agingIndexBase_f, &flow_hash_lookup_ctl, (96 + 96 + 192)*1024);
    SetFlowHashLookupCtl(V, flowHashLevel_4_agingIndexBase_f, &flow_hash_lookup_ctl, (96 + 96 + 192 + 192)*1024);
    SetFlowHashLookupCtl(V, flowHashLevel_5_agingIndexBase_f, &flow_hash_lookup_ctl, (96 + 96 + 192 + 192 + 256)*1024);
    SetFlowHashLookupCtl(V, flowHashCamAgingIndexBase_f, &flow_hash_lookup_ctl, (96 + 96 + 192 + 192 + 256 + 256 + 32 + 32)*1024);
    cmd = DRV_IOW(FlowHashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &flow_hash_lookup_ctl));

    /*x hash*/
    /*XLookup0Ctl_t...*/


    sys_usw_ftm_get_srv_aging_base(lchip, 0, &aging_base);

    cmd = DRV_IOR(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_engine_ctl));
    /* Ant Flow always use couple mode */
    SetLagEngineCtl(V, antFlowAgingBase_f, &lag_engine_ctl, aging_base);/* include cam but but not tcam */
    SetLagEngineCtl(V, antFlowAgingMode_f, &lag_engine_ctl, 1);/* Hw Aging */
    SetLagEngineCtl(V, antFlowAgingTimer_f, &lag_engine_ctl, SYS_AGING_TIMER_INDEX_RSV);
    cmd = DRV_IOW(LagEngineCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_engine_ctl));

    sys_usw_ftm_get_srv_aging_base(lchip, 1, &aging_base);
    cmd = DRV_IOR(IpeEcmpCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_ecmp_ctl));
     /* Ant Flow always use couple mode */
    SetIpeEcmpCtl(V, antFlowAgingBase_f, &ipe_ecmp_ctl, aging_base);/* include cam but but not tcam */
    SetIpeEcmpCtl(V, antFlowAgingMode_f, &ipe_ecmp_ctl, 1);/* Hw Aging */
    SetIpeEcmpCtl(V, antFlowAgingTimer_f, &ipe_ecmp_ctl, SYS_AGING_TIMER_INDEX_RSV);
    cmd = DRV_IOW(IpeEcmpCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_ecmp_ctl));



    sal_memset(ds, 0, sizeof(ds_t));
    SetIpeAgingSliceModeCtl(V, iAmMaster_f, &ds, 1);
    cmd = DRV_IOW(IpeAgingSliceModeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &ds));
    cmd = DRV_IOR(PpAgingMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &pp_aging_mode));
    SetPpAgingMode(V, coreAgingIndexValid_f, &pp_aging_mode, 1);
    SetPpAgingMode(V, iAmMaster_f, &pp_aging_mode, 0);
    cmd = DRV_IOW(PpAgingMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &pp_aging_mode));
    SetPpAgingMode(V, iAmMaster_f, &pp_aging_mode, 1);
    cmd = DRV_IOW(PpAgingMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &pp_aging_mode));

    if (dul_core_mode)
    {
        cmd = DRV_IOR(LearningCacheAgingCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetLearningCacheAgingCtl(V, agingInterval_f, &ds, 0x4E3B2920); /*30s*/
        SetLearningCacheAgingCtl(V, maxPtr_f, &ds, DRV_ENUM(DRV_LEARN_CACHE_NUM) - 1);
        SetLearningCacheAgingCtl(V, maxPhyPtr_f, &ds, DRV_ENUM(DRV_LEARN_CACHE_NUM) - 1);
        SetLearningCacheAgingCtl(V, scanEn_f, &ds, 1);
        cmd = DRV_IOW(LearningCacheAgingCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    }

    /* set dma callback for learning & aging module */
    CTC_ERROR_RETURN(sys_usw_dma_register_cb(lchip, SYS_DMA_CB_TYPE_LERNING, sys_at_learning_aging_sync_data));

    return CTC_E_NONE;
}
#endif

int32
sys_tmm_aging_get_aging_ptr(uint8 lchip, uint8 domain_type, uint32 key_index, uint32* aging_ptr)
{
    CTC_BIT_UNSET(domain_type, SYS_AGING_PP_EN_BIT); 
    if(domain_type < SYS_AGING_DOMAIN_NUM)
    {
        CTC_ERROR_RETURN(p_usw_la_master[lchip]->callbacks_get_ptr[domain_type](lchip, domain_type, key_index, aging_ptr));
        SYS_LEARNING_AGING_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "[Aging] key_index:%d, domain_type:%d, aging_ptr:%d\n",
                               key_index, domain_type, *aging_ptr);
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_tmm_aging_get_agingptr_base(uint8 lchip)
{
    uint8  level_id = 0;
    uint8  step1=0,step2=0,step3=0;
    uint32 cmd = 0;
    uint32 aging_offset = 0;
    ds_t ds;
    sys_aging_base_t* p_aging_base=NULL;
    sys_aging_base_t* p_aging_base_1=NULL;

    /*Mac hash*/
    p_aging_base = &p_usw_la_master[lchip]->aging_base[SYS_AGING_DOMAIN_MAC_HASH];
    cmd = DRV_IOR(FibAccelerationCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    step1 = FibAccelerationCtl_host0Level1MacHashEn_f - FibAccelerationCtl_host0Level0MacHashEn_f;
    step2 = FibAccelerationCtl_agingPtrDemarcation1_f - FibAccelerationCtl_agingPtrDemarcation0_f;
    step3 = FibAccelerationCtl_demarcationIndex1_f - FibAccelerationCtl_demarcationIndex0_f;
    for (level_id = 1; level_id < (DRV_IS_TMM(lchip)?7:6); level_id++)
    {
        p_aging_base->level_en[level_id] = GetFibAccelerationCtl(V, host0Level0MacHashEn_f + step1 * level_id, &ds);
        p_aging_base->aging_ptr_base[level_id] = GetFibAccelerationCtl(V, agingPtrDemarcation0_f + step2 * (level_id-1), &ds);
        p_aging_base->key_index_base[level_id] = GetFibAccelerationCtl(V, demarcationIndex0_f + step3 * (level_id-1), &ds);
    }
    p_aging_base->level_en[0] = GetFibAccelerationCtl(V, host0Level0MacHashEn_f, &ds);
    p_aging_base->aging_ptr_base[0] = 32;
    p_aging_base->key_index_base[0] = 32;
    p_aging_base->cam_ptr_base = 0;
    p_aging_base->key_index_base[level_id] = GetFibAccelerationCtl(V, demarcationIndex0_f + step3 * (level_id-1), &ds);

    /*Fib Host1*/
    p_aging_base = &p_usw_la_master[lchip]->aging_base[SYS_AGING_DOMAIN_HOST1];
    cmd = DRV_IOR(FibHost1HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    step1 = FibHost1HashLookupCtl_fibHost1Level_1_hashEn_f - FibHost1HashLookupCtl_fibHost1Level_0_hashEn_f;
    p_aging_base->cam_ptr_base = GetFibHost1HashLookupCtl(V, fibHost1AgingIndexOffset_f, &ds);
    aging_offset = p_aging_base->cam_ptr_base + 32;
    if (DRV_FROM_AT(lchip))
    {
        for (level_id = 0; level_id < 6; level_id++)
        {    
            p_aging_base->level_en[level_id] = GetFibHost1HashLookupCtl(V, fibHost1Level_0_hashEn_f + step1 * level_id, &ds);
            p_aging_base->aging_ptr_base[level_id] = GetFibHost1HashLookupCtl(V, fibHost1Level_0_agingIndexBase_f + step1 * level_id, &ds) + aging_offset;
            p_aging_base->key_index_base[level_id] = GetFibHost1HashLookupCtl(V, fibHost1Level_0_indexBase_f + step1 * level_id, &ds)+32;
        }
        p_aging_base->key_index_base[6] = p_aging_base->key_index_base[5] + 8192;
    }
    else
    {
        p_aging_base->level_en[0] = GetFibHost1HashLookupCtl(V, fibHost1Level0HashEn_f, &ds);
        p_aging_base->level_en[1] = GetFibHost1HashLookupCtl(V, fibHost1Level1HashEn_f, &ds);
        p_aging_base->level_en[2] = GetFibHost1HashLookupCtl(V, fibHost1Level2HashEn_f, &ds);
        p_aging_base->level_en[3] = GetFibHost1HashLookupCtl(V, fibHost1Level3HashEn_f, &ds);

        p_aging_base->key_index_base[1] = GetFibHost1HashLookupCtl(V, fibHost1Level1IndexBase_f, &ds)+32;
        p_aging_base->key_index_base[2] = GetFibHost1HashLookupCtl(V, fibHost1Level2IndexBase_f, &ds)+32;
        p_aging_base->key_index_base[3] = GetFibHost1HashLookupCtl(V, fibHost1Level3IndexBase_f, &ds)+32;
        p_aging_base->key_index_base[4] = p_aging_base->key_index_base[3] + 8192;

        p_aging_base->aging_ptr_base[1] = GetFibHost1HashLookupCtl(V, fibHost1Level1AgingIndexBase_f, &ds) + aging_offset;
        p_aging_base->aging_ptr_base[2] = GetFibHost1HashLookupCtl(V, fibHost1Level2AgingIndexBase_f, &ds) + aging_offset;
        p_aging_base->aging_ptr_base[3] = GetFibHost1HashLookupCtl(V, fibHost1Level3AgingIndexBase_f, &ds) + aging_offset;
    }


    /*IP hash*/
    p_aging_base = &p_usw_la_master[lchip]->aging_base[SYS_AGING_DOMAIN_IP_HASH];
    cmd = DRV_IOR(FibHost0HashLookupCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    if (DRV_FROM_AT(lchip))
    {
        p_aging_base->level_en[0] = GetFibHost0HashLookupCtl(V, fibHost0L3Level_0_hashEn_f, &ds);
        p_aging_base->level_en[1] = GetFibHost0HashLookupCtl(V, fibHost0L3Level_1_hashEn_f, &ds);
        p_aging_base->key_index_base[0] = GetFibHost0HashLookupCtl(V, fibHost0L3Level_0_indexBase_f, &ds)+32;
        p_aging_base->key_index_base[1] = GetFibHost0HashLookupCtl(V, fibHost0L3Level_1_indexBase_f, &ds)+32;
        p_aging_base->aging_ptr_base[0] = GetFibHost0HashLookupCtl(V, fibHost0L3Level_0_agingIndexBase_f, &ds);
        p_aging_base->aging_ptr_base[1] = GetFibHost0HashLookupCtl(V, fibHost0L3Level_1_agingIndexBase_f, &ds);
    }
    else
    {
        p_aging_base->level_en[0] = GetFibHost0HashLookupCtl(V, fibHost0L3Level0HashEn_f, &ds);
        p_aging_base->level_en[1] = GetFibHost0HashLookupCtl(V, fibHost0L3Level1HashEn_f, &ds);
        p_aging_base->key_index_base[0] = 32;
        p_aging_base->key_index_base[1] = GetFibHost0HashLookupCtl(V, fibHost0L3Level1IndexBase_f, &ds)+32;
        p_aging_base->aging_ptr_base[0] = GetFibHost0HashLookupCtl(V, fibHost0L3Level0AgingIndexBase_f, &ds);
        p_aging_base->aging_ptr_base[1] = GetFibHost0HashLookupCtl(V, fibHost0L3Level1AgingIndexBase_f, &ds);
    }
    p_aging_base->key_index_base[2] = p_aging_base->key_index_base[1]+(p_aging_base->aging_ptr_base[1] - p_aging_base->aging_ptr_base[0]);
    p_aging_base->cam_ptr_base = GetFibHost0HashLookupCtl(V, fibHost0IpCamLookupAgingIndexBase_f, &ds);


    /*LPM */
    step1 = NeoLpmCtl_group0Memory1AgingIndexBase_f - NeoLpmCtl_group0Memory0AgingIndexBase_f;
    step2 = NeoLpmCtl_group1Memory1AgingIndexBase_f - NeoLpmCtl_group1Memory0AgingIndexBase_f;
    p_aging_base = &p_usw_la_master[lchip]->aging_base[SYS_AGING_DOMAIN_LPM_HASH_GROUP0];
    p_aging_base_1 = &p_usw_la_master[lchip]->aging_base[SYS_AGING_DOMAIN_LPM_HASH_GROUP1];
    cmd = DRV_IOR(NeoLpmCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    
    for (level_id = 0; level_id < (DRV_IS_TMM(lchip)?5:4); level_id++)
    {
        p_aging_base->aging_ptr_base[level_id] = GetNeoLpmCtl(V, group0Memory0AgingIndexBase_f + step1 * level_id, &ds);
        p_aging_base_1->aging_ptr_base[level_id] = GetNeoLpmCtl(V, group1Memory0AgingIndexBase_f + step2 * level_id, &ds);        
    }
    p_aging_base->level_en[0] = GetNeoLpmCtl(V, memoryEn_f, &ds);
    p_aging_base->level_en[1] = GetNeoLpmCtl(V, memoryL0En_f, &ds);
    if (DRV_FROM_AT(lchip))
    {
        p_aging_base->aging_ptr_base[5] = GetNeoLpmCtl(V, group0L0Memory0AgingIndexBase_f, &ds);
        p_aging_base->aging_ptr_base[6] = GetNeoLpmCtl(V, group0L0Memory1AgingIndexBase_f, &ds);
        p_aging_base_1->aging_ptr_base[5] = GetNeoLpmCtl(V, group1L0Memory0AgingIndexBase_f, &ds);
        p_aging_base_1->aging_ptr_base[6] = GetNeoLpmCtl(V, group1L0Memory1AgingIndexBase_f, &ds);
    }
    
    return CTC_E_NONE;

}

int32 _sys_tmm_aging_cb_init(uint8 lchip)
{
    p_usw_la_master[lchip]->callbacks_get_ptr[SYS_AGING_DOMAIN_MAC_HASH] = sys_tmm_aging_get_hash_aging_ptr;
    p_usw_la_master[lchip]->callbacks_get_ptr[SYS_AGING_DOMAIN_IP_HASH] = sys_tmm_aging_get_hash_aging_ptr;
    p_usw_la_master[lchip]->callbacks_get_ptr[SYS_AGING_DOMAIN_TCAM] = _sys_usw_aging_get_tcam_aging_ptr;
    p_usw_la_master[lchip]->callbacks_get_ptr[SYS_AGING_DOMAIN_NAT_TCAM] = _sys_usw_aging_get_tcam_aging_ptr;
    p_usw_la_master[lchip]->callbacks_get_ptr[SYS_AGING_DOMAIN_HOST1] = sys_tmm_aging_get_hash_aging_ptr;
    p_usw_la_master[lchip]->callbacks_get_ptr[SYS_AGING_DOMAIN_LPM_HASH_GROUP0] = sys_tmm_aging_get_lpm_aging_ptr;
    p_usw_la_master[lchip]->callbacks_get_ptr[SYS_AGING_DOMAIN_LPM_HASH_GROUP1] = sys_tmm_aging_get_lpm_aging_ptr;
    return CTC_E_NONE;
}

int32 
sys_tmm_aging_init(uint8 lchip)
{
    uint32 tcam_aging_num = 0;
    sys_usw_ftm_query_table_entry_num(lchip, DsAgingStatusTcam_t, &tcam_aging_num);
    _sys_tmm_aging_get_level_free_agingptr_to_db(lchip, p_usw_la_master[lchip]->fib_free_ptr);
    p_usw_la_master[lchip]->aging_tcam_num = tcam_aging_num*32;
    _sys_tmm_aging_get_agingptr_base(lchip);
    _sys_tmm_aging_cb_init(lchip);
    
    
    return CTC_E_NONE;
}

#endif
